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SUMMARY:TILOS Seminar: Reasoning Numerically
DESCRIPTION:Sicun Gao\, Assistant Professor\, UC San Diego \nAbstract: Highly-nonlinear continuous functions have become a pervasive model of computation. Despite newsworthy progress\, the practical success of “intelligent” computing is still restricted by our ability to answer questions regarding their quality and dependability: How do we rigorously know that a system will do exactly what we want it to do and nothing else? For traditional software and hardware systems that primarily use digital and rule-based designs\, automated reasoning has provided the fundamental principles and widely-used tools for ensuring their quality in all stages of design and engineering. However\, the rigid symbolic formulations of typical automated reasoning methods often make them unsuitable for dealing with computation units that are driven by numerical and data-driven approaches. I will overview some of our attempts in bridging this gap. I will highlight how the core challenge of NP-hardness is shared across discrete and continuous domains\, and how it motivates us to seek the unification of symbolic\, numerical\, and statistical perspectives towards better understanding and handling of the curse of dimensionality.
URL:https://tilos.ai/event/reasoning-numerically/
LOCATION:Virtual
CATEGORIES:TILOS Seminar Series
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CREATED:20250904T171857Z
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SUMMARY:TILOS Seminar: The FPGA Physical Design Flow Through the Eyes of ML
DESCRIPTION:Dr. Ismail Bustany\, Fellow at AMD \nAbstract: The FPGA physical design (PD) flow has innate features that differentiate it from its sibling\, the ASIC PD flow. FPGA device families service a wide range of applications\, have much longer lifespans in production use\, and bring templatized logic layout and routing interconnect fabrics whose characteristics are captured by detailed device models and simpler timing and routing models (e.g. buffered interconnect and abstracted routing resources). Furthermore\, the FPGA PD flow is a “one-stop shop” from synthesis to bitstream generation. This avails complete access to annotate\, instrument\, and harvest netlist and design features. These key differences provide rich opportunities to exploit both device data and design application specific contexts in optimizing various components of the PD flow. In this talk\, I will present examples for the application of ML in device modeling and parameter optimization\, draw attention to exciting research opportunities for applying the “learning to optimize” paradigm to solving the placement and routing problems\, and share some practical learnings.
URL:https://tilos.ai/event/tilos-seminar-the-fpga-physical-design-flow-through-the-eyes-of-ml/
LOCATION:Virtual
CATEGORIES:TILOS Seminar Series
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