Artificial Netlist Generation
Integrated circuit (IC) design data is sparse, closely guarded, and always in flux with rapid evolution of architectures, standards and technologies. Release of “real” research data, especially at the level of gate-netlist and layout representations, is impossible since it exposes both design and technology information. This motivates the generation of artificial benchmark data to unblock research on CAD optimizations. Our goal is to develop scalable generators for artificial circuit netlists that are indistinguishable from real circuit netlists, from the perspective of CAD optimizations. To this end, we are focusing on artificial clip netlist generation that is usable in research on optimal embedding. We also develop enhanced methods for artificial and/or obfuscated gate-level netlist generation, to support the benchmarking and roadmapping of progress in placement, routing, sizing, or other core optimizations.
Artificial Netlist Generator 2.0 (ANG2.0). The ANG [1] package from POSTECH offers a convenient way of artificial netlist generation by getting only six parameters as an input. Considering the fact that a huge number of training data is required for physical design ML models, the capability of generating small size netlist with accurate target characteristics is a key feature for successful artificial netlist generators. To check this capability of ANG, target design (~288k instances) was scaled down to a small block (~28k instances) using ANG. However, it showed large performance and power gaps (480ps in timing, 8.5uW/um^2 in power). To reduce these gaps, we broke down netlist components and matched each component, resulting in 480ps→130ps (timing) and 8.5 uW/um^2 → 1.2 uW/um^2 (power) gap reductions. This improvement data gave “hints” for ANG2.0 research.
Figure 1. Scaled down (~10%) ANG block (left) and its performance-power gap reduction experiment result (right).
We also focus on the fact that most of the core designs include macros inside. To fulfill this requirement, a preliminary method of macro insertion was applied to the ANG. We applied this method in ML data generation for Tomography routing blockage model training. The concept of the Tomography routing blockage was introduced in [2]. Using this “macro-inserted” ANG, we could efficiently generate several types of small blocks with macros.
References
[1] D. Kim, S.-Y. Lee, K. Min, and S. Kang, Construction of realistic place-and-route benchmarks for machine learning applications, IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 42, no. 6, pp. 2030–2042, 2023.
[2] A. B. Kahng, Solvers, Engines, Tools and Flows: The Next Wave for AI/ML in Physical Design, Proc. ACM/IEEE Intl. Symp. on Physical Design, 2024.