Robust Watermarking for IC Physical Design IP Production
Physical design watermarking on contemporary integrated circuit (IC) layout encodes signatures without considering the dense connections and design constraints, which could lead to performance degradation on the watermarked products.
We develop ICMarks, a quality-preserving and robust watermarking framework for modern IC physical design. It embeds unique watermark signatures during the physical design's placement stage, thereby authenticating the IC layout ownership. ICMarks stands out among prior work by (i) strategically identifying a region of cells to watermark with minimal impact on the layout performance and (ii) employing a two-level watermarking framework for augmented robustness toward potential removal and forging attacks.
Extensive evaluations on benchmarks of different design objectives and sizes validate that ICMarks incurs no wirelength and timing metrics degradation, while successfully proving ownership. Furthermore, ICMarks is robust against two major watermarking attack categories, namely, watermark removal and forging attacks; even if the adversaries have prior knowledge of the watermarking schemes, the signatures cannot be removed without significantly undermining the layout quality. This work is under review in IEEE Transactions on Computer-Aided Design.
Figure 1. ICMarks framework. ICMarks first applies global watermarking during its global placement and then applies detailed watermarking on top of the watermarked region before the detailed placement.
Most recently we developed the ICMark methodology with both global and detailed watermarking. We evaluated our system’s performance on wirelength-driven ISPD’2015/ISPD’2019 benchmarks and timing-driven ICCAD’2015 benchmarks. Evaluation performance demonstrates ICMark maintains the watermarking fidelity.
We perform comprehensive robustness analysis showing ICMark can withstand various watermarking removal attacks and forging attacks. Even if the adversaries have prior knowledge of the watermarking schemes, the signatures cannot be removed without significantly undermining the layout quality. This work is under review in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
Next we plan to automate the watermarked region and cell selection and reduce the overhead for watermark search by leveraging machine learning tools, e.g., graph neural networks.