Chip design has long inspired optimization innovations, from simulated annealing to randomized rounding and spectral embedding. Key challenges include hierarchical-system context; the extreme cost of training data; “multi-everything” constrained optimization (where “multi” spans from underlying physics to objective functions); and pervasive security aspects.

The enormous scale and complexity of chip design optimizations motivate research to answer such questions as: How can we discover exploitable structure in cost landscapes? Can we apply distributed, data-driven sampling and search methods to obtain better designs in less time? And, what are the metaheuristic “templates” that will help match discovered instance structure to best-performing optimization strategies? Optimizing hierarchical, physical systems also demands communication of lower-level abstractions to higher-level optimizations, e.g., via statistical learning of low-dimensional representations that can be reused across search spaces. Last, chip design is also a testbed for augmenting rather than rediscovering domain expertise, by encoding expert knowledge and intuition to serve optimization and decision-making agents.

The team’s initial research targets include: (i) creating chip layouts directly from circuit descriptions; (ii) discovering the next scaling breakthroughs in verification; and (iii) quantifying the cost of “X”, in particular for X = security.