Research Thrust 3: AI Hardware Substrate

This thrust builds a closed-loop, AI-native hardware–software ecosystem that tightly integrates AI for hardware design with hardware for AI. Continuous co-optimization across design time, compile time, and run time lets hardware, models, and system software evolve together, enabling next-generation platforms for domains such as robotics.

TILOS Publications on Google Scholar (opens in a new tab)

Theme H1AI-Native Chip Design and EDA

Moving electronic design automation beyond heuristic, stage-wise flows toward global optimization for digital, analog/RF, and 3D integrated systems.

Research directions

  • Unified AI-native EDA framework
  • Generative AI for analog/RF designs
  • Physical AI for 3D integrated systems

Faculty

David Z. Pan, Farinaz Koushanfar, Sensen Li, Alejandro Ribeiro, Yusu Wang

Project highlights for this theme are coming soon.

Theme H2Adaptive, Multimodal, and Robust AI Accelerators

Accelerator and system design for embodied and multimodal AI under tight energy, latency, and reliability constraints.

Research directions

  • New computing paradigms for multimodal learning and inference
  • Novel interconnect technologies
  • Hardware/workload co-design

Faculty

Tajana Rosing, Farinaz Koushanfar, Sensen Li, David Z. Pan, Peipei Zhou, Arya Mazumdar

Project highlights for this theme are coming soon.

Theme H3AI-Agent-Driven Programming, Compilation, and Runtime for Heterogeneous AI Systems

New abstractions and agent-driven runtimes that manage increasingly heterogeneous hardware and close the loop between chip design and deployment.

Research directions

  • New programming models and abstractions for heterogeneous AI systems
  • AI-agent-driven runtime systems for adaptive orchestration and co-design

Faculty

Peipei Zhou, David Z. Pan, Tajana Rosing, Farinaz Koushanfar, Yury Polyanskiy

Project highlights for this theme are coming soon.

Theme H4Security, Reliability, and Traceability

End-to-end trust for AI-driven chip design, addressing new risks in correctness, security, and intellectual property protection.

Research directions

  • Proofs of signature provenance for hardware IP protection
  • Secure and integrated AI-EDA pipelines with formal guarantees and confidential computing

Faculty

Farinaz Koushanfar, David Z. Pan, Tajana Rosing, Peipei Zhou, Yu-Xiang Wang

Project highlights for this theme are coming soon.