IEEE Seasonal School: Manufacturability, Testing, Reliability, and Security
00:00:00 - Introduction
01:51:00 - "Machine Learning for DFM", Bei Yu, Associate Professor, Chinese University of Hong Kong
59:54:00 - "ML for Testing and Yield", Li-C. Wang, Professor, UC Santa Barbara
01:59:00 - "ML for Cross-Layer Reliability and Security", Muhammad Shafique, Professor of Computer Engineering, NYU Abu Dhabi
IEEE Seasonal School: Standard Platforms for ML in EDA and IC Design
00:00:00 - Introduction
00:02:45 - "Exchanging EDA data for AI/ML using Standard API", Kerim Kalafala, Senior Technical Staff Member, IBM (co-chair, AI/ML for EDA Special Interest Group, Si2), Richard Taggart, Senior Software Engineering Manager, IBM and Akhilesh Kumar, Principal R&D Engineer, Ansys
01:29:30 - "IEEE CEDA DATC RDF and METRICS2.1: Toward a Standard Platform for ML-Enabled EDA and IC Design", Jinwook Jung, Research Staff Member, IBM Research
IEEE Seasonal School: Applications / Future Frontiers
00:00:00 - Introduction
01:23:00 - "Automating Analog Layout: Why This Time is Different", Sachin Sapatnekar, Professor, University of Minnesota
57:20:00 - "Machine Learning-Powered Tools and Methodologies for 3D Integration", Sung Kyu Lim, Professor, Georgia Institute of Technology
01:58:18 - "ML for Verification", Shobha Vasudevan, Researcher at Google and Adjunct Professor at UIUC
IEEE Seasonal School: Deep / Reinforcement Learning
00:00:00 - Introduction
02:30:00 - "Machine Learning for EDA Optimization", Mark Ren, Senior Manager, NVIDIA Research
01:02:30 - "Learning to Optimize", Ismail Bustany, Fellow, AMD
02:01:50 - "Circuit Training: An open-source framework for generating chip floor plans with distributed deep reinforcement learning", Joe Jiang, Staff Software Engineer and Manager, Google Brain
TILOS Seminar: Machine Learning for Design Methodology and EDA Optimization
Haoxing Ren, NVIDIA
In this talk, I will first illustrate how ML helps improve design quality as well as design productivity from design methodology perspective with examples in digital and analog designs. Then I will discuss the potential of applying ML to solve challenging EDA optimization problems, focusing on three promising ML techniques: reinforcement learning (RL), physics-based modeling and self-supervised learning (SSL). RL learns to optimize the problem by converting the EDA problem objectives into environment rewards. It can be applied to both directly solve the EDA problem or be part of a conventional EDA algorithm. Physics-based modeling enables more accurate and transferable learning for EDA problems. SSL learns the optimized EDA solution data manifold. Conditioned on the problem input, it can directly produce the solution. I will illustrate the applications of these techniques in standard cell layout, computational lithography, and gate sizing problems. Finally, I will outline three main approaches to integrate ML and conventional EDA algorithms together and the importance of adopting GPU computing to EDA.
Haoxing Ren (Mark) leads the Design Automation research group at NVIDIA Research. His research interests are machine learning applications in design automation and GPU accelerated EDA. Before joining NVIDIA in 2016, he spent 15 years at IBM Microelectronics and IBM Research working on physical design and logic synthesis tools and methodologies for IBM microprocessor and ASIC designs. He received several IBM technical achievement awards including the IBM Corporate Award for his work on improving microprocessor design productivity. He published many papers in the field of design automation including several book chapters in logic synthesis and physical design. He also received the best paper awards at ISPD’2013, DAC’2019 and TCAD’2021. He earned his PhD in Computer Engineering from University of Texas at Austin in 2006.
The FPGA Physical Design Flow Through the Eyes of Machine Learning
Dr. Ismail Bustany, Fellow, AMD
The FPGA physical design (PD) flow has innate features that differentiate it from its sibling, the ASIC PD flow. FPGA device families service a wide range of applications, have much longer lifespans in production use, and bring templatized logic layout and routing interconnect fabrics whose characteristics are captured by detailed device models and simpler timing and routing models (e.g. buffered interconnect and abstracted routing resources). Furthermore, the FPGA PD flow is a “one-stop shop” from synthesis to bitstream generation. This avails complete access to annotate, instrument, and harvest netlist and design features. These key differences provide rich opportunities to exploit both device data and design application specific contexts in optimizing various components of the PD flow. In this talk, I will present examples for the application of ML in device modeling and parameter optimization, draw attention to exciting research opportunities for applying the “learning to optimize” paradigm to solving the placement and routing problems, and share some practical learnings.
Dr. Ismail Bustany is a Fellow at AMD, where he works on physical design implementation and MLCAD . He has served on the technical program committees for the ISPD, ISQED, and DAC. He was the 2019 ISPD general chair. He currently serves on the organizing committees for the ICCAD and SLIP. He organized the 2014 and 2015 ISPD detailed routing-driven placement contests and co-organized the 2017 ICCAD detailed placement contest. His research interests include physical design, computationally efficient optimization algorithms, MLCAD, sparse matrix computations/acceleration, and partitioning algorithms. He earned his B.S. in CSE from UC San Diego and M.S./Ph.D. in EECS from UC Berkeley.
TILOS Seminar: Closing the Virtuous Cycle of AI for IC and IC for AI
David Pan, Professor, University of Texas at Austin
The recent artificial intelligence (AI) boom has been primarily driven by three confluence forces: algorithms, big-data, and computing power enabled by modern integrated circuits (ICs), including specialized AI accelerators. This talk will present a closed-loop perspective for synergistic AI and agile IC design with two main themes, AI for IC and IC for AI. As semiconductor technology enters the era of extreme scaling and heterogeneous integration, IC design and manufacturing complexities become extremely high. More intelligent and agile IC design technologies are needed than ever to optimize performance, power, manufacturability, design cost, etc., and deliver equivalent scaling to Moore’s Law. This talk will present some recent results leveraging modern AI and machine learning advancement with domain-specific customizations for agile IC design and manufacturing, including open-sourced DREAMPlace (DAC’19 and TCAD’21 Best Paper Awards), DARPA-funded MAGICAL project for analog IC design automation, and LithoGAN for design-technology co-optimization. Meanwhile on the IC for AI frontier, customized ICs, including those with beyond-CMOS technologies, can drastically improve AI performance and energy efficiency by orders of magnitude. I will present our recent results on hardware and software co-design for optical neural networks and photonic ICs (which won the 2021 ACM Student Research Competition Grand Finals 1st Place). Closing the virtuous cycle between AI and IC holds great potential to significantly advance the state-of-the-art of each other.