Artificial Netlist Generation Integrated circuit (IC) design data is sparse, closely guarded, and always in flux with rapid evolution of architectures, standards and technologies. Release of “real” research data, especially at the level of gate-netlist and layout representations, is impossible since it exposes both design and technology information. This motivates the generation of artificial benchmark […]
Robust Watermarking for IC Physical Design IP Production Physical design watermarking on contemporary integrated circuit (IC) layout encodes signatures without considering the dense connections and design constraints, which could lead to performance degradation on the watermarked products. We develop ICMarks, a quality-preserving and robust watermarking framework for modern IC physical design. It embeds unique watermark […]
Interior Search for Nonlinear SMT and Application in Verification Surface-mount technology (SMT) formulas over the real numbers can encode a wide range of problems in theorem proving and formal verification. Currently, constraint solving and verification in nonlinear theories over the reals use strategies that are similar to SAT solving. The current algorithms perform top-down global […]
Better Search Methods for Derivative-free Optimization Non-convex global optimization problems are well-known to be NP-hard, and the practical challenge lies in distinguishing the global optimum from exponentially many potential local optima. Existing approaches to non-convex optimization can be largely categorized into sampling-based methods and tree-search methods. Sampling-based approaches explore the solution space through random sampling […]
Nexus of Sampling, Sequential Decision-making, L2O and Cloud Today’s IC design optimizations were developed for pre-cloud era compute infrastructure of the 1980s and 1990s. We seek to reinvent CAD optimizations in a {sampling, L2O, federated, cloud} context. We apply distributed sampling and sequential decision-making methods to core optimizations, starting from detailed routing and concurrent placement […]
Modern Hypergraph Partitioning Balanced hypergraph partitioning is a well-studied, fundamental combinatorial optimization problem with multiple applications in EDA. The objective is to partition vertices of a hypergraph into a specified number of disjoint blocks such that each block has bounded size and the cutsize, i.e., the number of hyperedges spanning multiple blocks, is minimized. In […]
Optimal Embedding: HypOp Combinatorial optimization is ubiquitous across science and industry. In recent years, the integration of artificial intelligence (AI) into the field of scientific discovery is growing increasingly fluid, providing means to enhance and accelerate research. An approach to integrate AI into scientific discovery involves leveraging machine learning (ML) methods to expedite and improve […]
Optimal Embedding Embedding refers to the placement and routing of a netlist hypergraph into a 3-D chip layout, as well as layout-related optimizations to minimize area, power and delay metrics while satisfying layout constraints (design rules), etc. In this topic, the ultimate goal is to scale the capacity and speed of optimal and near-optimal solvers […]
